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CDP1824, CDP1824C
March 1997
32-Word x 8-Bit Static RAM
Description
The CDP1824 and CDP1824C are 32-word x 8-bit fully static CMOS random-access memories for use in CDP-1800 series microprocessor systems. These parts are compatible with the CDP1802 microprocessor and will interface directly without additional components. The CDP1824 is fully decoded and does not require a precharge or clocking signal for proper operation. It has common input and output and is operated from a single voltage supply. The MRD signal (output disable control) enables the three-state output drivers, and overrides the MWR signal. A CS input is provided for memory expansion. The CDP1824C is functionally identical to the CDP1824. The CDP1824 has an operating range of 4V to 10.5V, and the CDP1824C has an operating voltage range of 4V to 6.5V. The CDP1824 and CDP1824C are supplied in 18 lead hermetic dual-in-line ceramic packages (D suffix), and in 18 lead dual-in-line plastic packages (E suffix).
Features
* Fast Access Time - VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710ns - VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320ns * No Precharge or Clock Required
Ordering Information
5V CDP1824CE CDP1824CEX CDP1824CD CDP1824E CDP1824EX CDP1824D 10V PDIP Burn-In SBDIP -40oC to +85oC PACKAGE TEMPERATURE RANGE -40oC to +85oC PKG. NO. E18.3 E18.3 D18.3
Pinout
CDP1824, CDP1824C (PDIP, SBDIP) TOP VIEW FUNCTION
MA4 MA3 MA2 MA1 MA0 BUS 7 BUS 6 BUS 5 VSS 1 2 3 4 5 6 7 8 9 18 VDD 17 MWR 16 MRD 15 CS 14 BUS 0 13 BUS 1 12 BUS 2 11 BUS 3 10 BUS 4
OPERATIONAL MODES CS 0 0 1 0 MRD MWR 0 1 X 1 X 0 X 1 DATA PINS STATUS Output: High/Low Dependent on Data Input: Output Disabled Output Disabled: High-Impedance State Output Disabled: High-Impedance State
READ WRITE Not Selected Standby Logic 1 = High
Logic 0 = Low X = Don't Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1103.2
6-37
CDP1824, CDP1824C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1824 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1824C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 75 20 PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Recommended Operating Conditions
At TA = Full Package Temperature Range.For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CONDITION CDP1824D LIMITS CDP1824CD MIN 4 VSS MAX 6.5 VDD 5 UNITS V V s s
PARAMETER Supply Voltage Range Recommended Input Voltage Range Input Signal Rise or Fall Time (Note 1) tR, tF NOTE:
VDD (V) 5 10
MIN 4 VSS -
MAX 10.5 VDD 5 2
1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode.
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted: CONDITIONS CDP1824 LIMITS CDP1824C MAX 50 500 0.1 0.1 1.5 3 1 1 8 16 MIN 1.8 -0.9 4.9 3.5 (NOTE 1) TYP 100 2.2 -1.1 0 5 0.1 4 MAX 200 0.1 1.5 1 8 UNITS A A mA mA mA mA V V V V V V V V A A mA mA
PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage
SYMBOL IDD
VO (V) -
VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10
VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10
MIN 1.8 3.6 -0.9 -1.8 4.9 9.9 3.5 7 -
(NOTE 1) TYP 25 250 2.2 4.5 -1.1 -2.2 0 0 5 10 0.1 0.1 4 8
IOL
0.4 0.5
IOH
4.6 9.5
VOL
-
VOH
-
VIL
0.5, 4.5 1.9
Input High Voltage
VIH
0.5, 9.5 1.9
Input Leakage Current
IIN
Any Input -
Operating Current (Note 2)
IDD1
6-38
CDP1824, CDP1824C
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted: (Continued) CONDITIONS CDP1824 PARAMETER Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1s. SYMBOL IOUT VO (V) 0, 5 0, 10 CIN COUT VIN (V) 0, 5 0, 10 VDD (V) 5 10 MIN (NOTE 1) TYP 0.2 0.2 5 10 MAX 2.0 2.0 7.5 15 MIN LIMITS CDP1824C (NOTE 1) TYP 0.2 5 10 MAX 2 7.5 15 UNITS A A pF pF
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, Input tR, tF = 10ns, CL = 50pF, RL = 200k; See Figure 1 LIMITS CDP1824D, CDP1824E (NOTE 1) (NOTE 2) MIN TYP MAX CDP1824CD, CDP1824CE (NOTE 1) (NOTE 2) MIN TYP MAX UNITS
TEST CONDITIONS PARAMETER READ OPERATION Access Time From Address Change Access Time From Chip Select Output Active From MRD tAA 5 10 tDOA 5 10 tAM 5 10 NOTES: SYMBOL VDD (V)
-
400 200 300 150 300 150
710 320 710 320 710 320
-
400 300 300 -
710 710 710 -
ns ns ns ns ns ns
1. Time required by a limit device to allow for the indicated function. 2. Time required by a typical device to allow for the indicated function. Typical values are for TA = +25oC and nominal VDD.
tAM (NOTE 1) tAA MA CS (NOTE 1) tDOA DATA OUT HIGH IMPEDANCE
MRD
NOTES: 1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output. FIGURE 1. READ CYCLE TIMING DIAGRAMS
6-39
CDP1824, CDP1824C
Dynamic Electrical Specifications
at TA = -40oC to +85oC, VDD 5%, Input tR, tF = 10ns, CL = 50pF, RL = 200k; See Figure 2 LIMITS CDP1824D, CDP1824E (NOTE 1) (NOTE 2) MIN TYP MAX CDP1824CD, CDP1824CE (NOTE 1) (NOTE 2) MIN TYP MAX UNITS
TEST CONDITIONS PARAMETER WRITE OPERATION Write Pulse Width tWRW 5 10 Data Setup Time tDS 5 10 Data Hold Time tDH 5 10 Chip Select Setup Time tCS 5 10 Address Setup Time tAS 5 10 NOTES: SYMBOL VDD (V)
390 180 390 180 70 35 425 215 640 390
200 150 100 50 40 20 210 110 500 300
-
390 390 70 425 640 -
200 100 40 210 500 -
-
ns ns ns ns ns ns ns ns ns ns
1. Time required by a limit device to allow for the indicated function. 2. Time required by a typical device to allow for the indicated function. Typical values are for TA = +25oC and nominal VDD.
MA tAS CS tCS tWRW MWR tDS BUS tDH
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
DATA RETENTION MODE VDD tCDR 0.95 VDD VDR tF (NOTE 1) tR (NOTE 1) tRC 0.95 VDD
VIH CS V IL
VIH VIL
NOTE: tR, tF > 1s. FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
6-40
CDP1824, CDP1824C
Data Retention Specifications
at TA = -40oC to +85oC; See Figure 3 TEST CONDITIONS VDD (V) VDR = 2.5V VDR = 2.5V 5 10 tRC VDR = 2.5V 5 10 CDP1824 MIN 2.5 600 300 600 300 MAX 10 LIMITS CDP1824C MIN 2.5 600 600 MAX 40 UNITS V A ns ns ns ns
PARAMETER Data Retention Voltage Data Retention Quiescent Current Chip Deselect to Data Retention Time Recovery to Normal Operation Time
SYMBOL VDR IDD tCDR
MA4 MA3 MA2 MA1 MA0 3 4 5
2
1 32 X 8-BIT ARRAY
ADDRESS DECODER
SENSE AMPL
MWR
17 I/O BUFFERS
16 MRD
CS VDD = 18 VSS = 9
15 6 7 8 10 11 12 13 14
BUS BUS BUS BUS BUS BUS BUS BUS 7 6 5 4 3 2 1 0
FIGURE 4. FUNCTIONAL DIAGRAM
CPU/ROM SYSTEM
RAM SYSTEM
ADDRESS
MA0-MA7 TPA MRD MWR CPU CDP1802 BUS0-BUS7
MA0-MA7 TPA MRD
MA0-MA7
MRD ROM CE0 BUS0-BUS7 MWR RAM CDP1824 CS BUS0-BUS7
DATA
FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)
6-41
CDP1824, CDP1824C
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
6-42

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